1. Field of the Invention
The present invention provides an electrically erasable programmable logic device, and more specifically, an erasable programmable logic device with reduced volume, which makes use of the standard COMS layout process.
2. Description of the Prior Art
With demands for portable electrical products in recent years, techniques of manufacturing electrically erasable programmable read-only memories (EEPROMs) have matured and the market has expanded. EEPROMs can be applied in digital cameras, video game consoles, personal digital assistants, telephone recording devices, and programmable IC products. An EEPROM is a non-volatile memory, which changes threshold voltages of transistors or memory cells to control opening and closing of corresponding gate channels to store memory data protected from loss because of power shutdown.
A prior art EEPROM uses a stacked gate technique wherein a memory cell is located on a substrate, and is composed of a drain, a source, and a stacked gate. The stacked gate is usually composed of a floating gate and a select gate wherein a double oxide layer isolates the floating gate and the substrate, the select gate and the floating gate. The stacked gate technique used in EEPROM applies a high potential voltage to the select gate to change stored electron amounts in the floating gate by electron FN tunneling effects or hot electrons injection which eventually changes the threshold voltage of the select gate and records data.
However, the structure of memory cells applied in EEPROM with a stacked gate technique is complicated to be generated by a standard complementary metal oxide semiconductor (CMOS) layout processing, and requires a more costly and complex processing. Therefore, the prior art, which is disclosed by R. Kazerounian and B. Eitann, xe2x80x9cA single-poly EPROM for custom CMOS logic applicationsxe2x80x9d, IEEE Custom Integrated Circuits Conference, p.59-62, 1986, claims another structure of single-poly memory cell. Please refer to FIG. 1. Illustrated in FIG. 1 is a lateral sectional diagram of a prior art single-poly memory cell 10, which is located on a substrate 12. An n-well is provided to be a coupling gate for a floating gate 16 in order to couple a high potential voltage, 9 to 12V, to the floating gate 16 through the coupling gate and further to generate channel hot electrons in the substrate 12 beneath the floating gate 16. By injection of the channel hot electrons to the floating gate 16, threshold potential of the floating gate will be altered which results in programming the memory cell 10. Because the single-poly structure is simple, it can be generated with standard COMS layout processing instead of the costly stacked gates technique.
There is still a major defect in the prior art single-poly memory cell 10: a large N-type well 14 having a relatively large area measure has to be applied to couple high potential voltage to the floating gate 16. The area measure of the N-type well is larger than other parts of the memory cell by 10 or more times which prevents the memory volume applied with the single-poly memory cell 10 from being reduced.
It is therefore a primary objective of the claimed invention to provide a electrically erasable programmable logic device that stores data by applying single-poly cell memory which is provided with a floating gate and a floating doped region to overcome the problems of the prior art.
According to the claims of the present invention, an electrically erasable programmable logic device is claimed to be applied as a memory cell. The electrically erasable programmable logic device comprises a P-type substrate, a N-type doped region located in the P-type substrate, a first gate being in a floating state located on the P-type substrate adjacent to the N-type doped region and used to store data of the electrically erasable programmable logic device, a second N-type doped region being in a floating state located in the P-type substrate adjacent to the first gate, a second gate adjacent to the second N-type doped region being a select gate of the electrically erasable programmable logic device, and a third N-type doped region located in the P-type substrate adjacent to the second gate.
An electrically erasable programmable logic device of the present invention applies a second gate to control voltage potential of a second N-type doped region in order to further control voltage potential of a first gate in order to generate channel hot holes or channel hot electrons in a P-type substrate under the first gate. The channel hot hole or channel hot electrons can be applied to change the threshold of the first gate to alter data stored in the logic device.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.